前言
第1 章　計(jì)算機(jī)系統(tǒng)概論 ·········· 1
1.1　計(jì)算機(jī)發(fā)展簡(jiǎn)史 ······················· 1
1.1.1　計(jì)算機(jī)的產(chǎn)生及發(fā)展 ········ 1
1.1.2　計(jì)算機(jī)的分類 ················ 3
1.1.3　計(jì)算機(jī)的應(yīng)用場(chǎng)景 ·········· 7
1.1.4　計(jì)算機(jī)的發(fā)展趨勢(shì) ·········· 9
1.2　計(jì)算機(jī)系統(tǒng)簡(jiǎn)介 ····················· 10
1.2.1　軟硬件系統(tǒng) ·················· 10
1.2.2　計(jì)算機(jī)層次結(jié)構(gòu) ············ 11
1.3　計(jì)算機(jī)系統(tǒng)的硬件組成 ············ 13
1.3.1　馮·諾依曼原理 ············ 13
1.3.2　計(jì)算機(jī)的硬件組成 ········· 15
1.4　計(jì)算機(jī)系統(tǒng)的性能指標(biāo) ············ 17
1.5　習(xí)題 ··································· 19
第2 章　計(jì)算機(jī)中數(shù)的表示 ····· 20
2.1　進(jìn)位計(jì)數(shù)制及進(jìn)制轉(zhuǎn)換 ············ 20
2.2　數(shù)的符號(hào)表示 ························ 22
2.2.1　無(wú)符號(hào)數(shù)表示 ··············· 22
2.2.2　有符號(hào)數(shù)表示 ··············· 23
2.2.3　 BCD 碼 ······················· 26
2.2.4　字符數(shù)據(jù)表示 ··············· 28
2.3　數(shù)的定點(diǎn)表示和浮點(diǎn)表示 ········· 30
2.3.1　定點(diǎn)表示 ····················· 31
2.3.2　浮點(diǎn)表示 ····················· 31
2.4　實(shí)例：IEEE 754 標(biāo)準(zhǔn) ·············· 34
2.5　數(shù)據(jù)校驗(yàn) ······························ 36
2.5.1　奇偶校驗(yàn)碼 ·················· 36
2.5.2　海明校驗(yàn)碼 ·················· 37
2.5.3　循環(huán)冗余校驗(yàn)碼 ············ 39
2.6　習(xí)題 ··································· 41
第3 章　運(yùn)算單元設(shè)計(jì) ··········· 44
3.1　邏輯運(yùn)算和移位運(yùn)算 ··············· 44
3.1.1　基本邏輯運(yùn)算 ··············· 44
3.1.2　移位運(yùn)算 ····················· 45
3.2　定點(diǎn)運(yùn)算 ······························ 48
3.2.1　加減法運(yùn)算 ·················· 48
3.2.2　乘法運(yùn)算 ····················· 52
3.2.3　除法運(yùn)算 ····················· 63
3.3　浮點(diǎn)運(yùn)算 ······························ 69
3.3.1　加減法運(yùn)算 ·················· 70
3.3.2　乘除法運(yùn)算 ·················· 72
3.4　算術(shù)邏輯單元（ALU） ············· 75
3.4.1　 并行加法器與快速進(jìn)
位鏈 ··························· 75
3.4.2　ALU 單元 ···················· 80
3.5　習(xí)題 ··································· 81
第4 章　存儲(chǔ)器系統(tǒng) ·············· 84
4.1　存儲(chǔ)器的分類及層次結(jié)構(gòu) ········· 84
4.1.1　存儲(chǔ)器的分類 ··············· 84
4.1.2　存儲(chǔ)器的層次結(jié)構(gòu) ········· 85
4.2　主存儲(chǔ)器 ······························ 87
4.2.1　概述 ··························· 87
4.2.2　隨機(jī)存儲(chǔ)器（RAM） ······· 92
4.2.3　只讀存儲(chǔ)器（ROM） ······· 98
4.2.4　存儲(chǔ)器與CPU 的連接 ··· 104
4.2.5　存儲(chǔ)器的擴(kuò)展 ············· 105
4.3　高速緩沖存儲(chǔ)器（Cache） ······· 111
4.3.1　概述 ························· 111
4.3.2　Cache 的工作原理 ········ 112
目　錄 V
4.3.3　Cache 的調(diào)度與替換 ····· 114
4.4　虛擬存儲(chǔ)器 ·························· 117
4.4.1　頁(yè)式虛擬存儲(chǔ)器 ·········· 118
4.4.2　段式虛擬存儲(chǔ)器 ·········· 119
4.4.3　段頁(yè)式虛擬存儲(chǔ)器 ······· 120
4.5　輔助存儲(chǔ)器 ·························· 121
4.5.1　 磁記錄原理與記錄
方式 ························· 121
4.5.2　硬磁盤存儲(chǔ)器 ············· 123
4.5.3　光盤及其他輔助存儲(chǔ)器 ·· 125
4.6　習(xí)題 ·································· 127
第5 章　指令系統(tǒng) ················ 130
5.1　機(jī)器指令 ····························· 130
5.1.1　指令格式 ··················· 130
5.1.2　指令的操作碼 ············· 131
5.1.3　指令的地址碼 ············· 132
5.1.4　指令字長(zhǎng) ··················· 134
5.2　指令類型與數(shù)據(jù)類型 ·············· 135
5.2.1　指令類型 ··················· 135
5.2.2　數(shù)據(jù)類型 ··················· 138
5.3　尋址方式 ····························· 140
5.3.1　指令尋址 ··················· 140
5.3.2　數(shù)據(jù)尋址 ··················· 141
5.3.3　尋址方式綜合例題 ······· 148
5.4　RISC 技術(shù) ··························· 150
5.4.1　RISC 的原理 ··············· 150
5.4.2　RISC 的特點(diǎn) ··············· 151
5.4.3　RISC 與CISC 的比較 ···· 152
5.5　習(xí)題 ·································· 152
第6 章　CPU 的結(jié)構(gòu)與設(shè)計(jì) ··· 156
6.1　CPU 的功能和組成 ················ 156
6.1.1　CPU 的功能 ················ 156
6.1.2　CPU 的組成 ················ 158
6.2　多級(jí)時(shí)序與時(shí)序系統(tǒng) ·············· 165
6.2.1　時(shí)序控制方式 ············· 165
6.2.2　指令周期與多級(jí)時(shí)序 ····· 167
6.3　組合邏輯控制器設(shè)計(jì) ·············· 171
6.3.1　模型機(jī)基本設(shè)計(jì) ·········· 172
6.3.2　微操作的節(jié)拍安排 ······· 174
6.3.3　 模型機(jī)組合邏輯控制器
設(shè)計(jì) ························· 176
6.4　微程序控制器設(shè)計(jì) ················· 179
6.4.1　微程序基本原理 ·········· 179
6.4.2　 微程序控制器基本
結(jié)構(gòu) ························· 180
6.4.3　微指令格式設(shè)計(jì) ·········· 181
6.4.4　模型機(jī)微程序設(shè)計(jì) ······· 185
6.5　改進(jìn)與提升CPU 性能的技術(shù) ··· 189
6.5.1　流水線技術(shù) ················ 189
6.5.2　同步多線程與超線程 ····· 195
6.5.3　多核技術(shù) ··················· 195
6.6　習(xí)題 ·································· 196
第7 章　系統(tǒng)總線 ················ 199
7.1　概述 ·································· 199
7.1.1　總線的基本概念 ·········· 199
7.1.2　總線的分類 ················ 200
7.1.3　 總線的特性和性能
指標(biāo) ························· 201
7.2　總線結(jié)構(gòu)和總線標(biāo)準(zhǔn)化 ··········· 203
7.2.1　單總線結(jié)構(gòu) ················ 203
7.2.2　多總線結(jié)構(gòu) ················ 205
7.2.3　總線的標(biāo)準(zhǔn)化 ············· 208
7.3　總線控制 ····························· 211
7.3.1　總線的判優(yōu)控制 ·········· 211
7.3.2　 總線的通信控制及信息
傳送方式 ··················· 213
7.4　習(xí)題 ·································· 218
第8 章　輸入輸出系統(tǒng) ·········· 221
8.1　I/O 設(shè)備 ······························ 221
8.1.1　I/O 設(shè)備的分類 ············ 221
8.1.2　輸入設(shè)備 ··················· 222
8.1.3　輸出設(shè)備 ··················· 224
8.1.4　其他I/O 設(shè)備 ·············· 233
8.2　I/O 接口 ······························ 236
VI 計(jì)算機(jī)組成原理
8.2.1　接口的概念 ················ 236
8.2.2　 主機(jī)與I/O 設(shè)備的信息
交換 ························· 236
8.2.3　接口的功能 ················ 237
8.2.4　接口的結(jié)構(gòu) ················ 238
8.2.5　接口的編址方式 ·········· 238
8.3　程序直接控制方式 ················· 239
8.3.1　無(wú)條件傳送方式 ·········· 239
8.3.2　條件傳送方式 ············· 239
8.4　程序中斷方式 ······················· 242
8.4.1　中斷的基本概念 ·········· 242
8.4.2　中斷的處理過(guò)程 ·········· 243
8.4.3　 程序中斷方式接口電路
和I/O 中斷的處理過(guò)程 ·· 247
8.5　DMA 方式 ··························· 248
8.5.1　DMA 方式的基本概念 ··· 248
8.5.2　DMA 傳送方式 ············ 249
8.5.3　 DMA 控制器的組成及
功能 ························· 250
8.5.4　DMA 的工作過(guò)程 ········· 252
8.5.5　 DMA 控制器與系統(tǒng)的
連接方式 ··················· 253
8.5.6　 選擇型和多路型DMA
控制器 ······················ 254
8.5.7　DMA 方式的特點(diǎn) ········· 256
8.6　習(xí)題 ·································· 256
附錄 ·································· 258
附錄A　基本邏輯門電路 ··············· 258
附錄B　組合邏輯器件 ·················· 258
附錄C　基本時(shí)序電路 ·················· 260
參考文獻(xiàn) ···························· 262